Santa Clara, CA, United States of America

William Chin

This inventor holds 1 USPTO granted patent. Top assignee: Applied Materials, Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: William Chin. Retrieved from https://idiyas.com/inventor/william-chin-yvjrwtuq

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: William Chin and Plasma Processing Innovation.

Introduction

William Chin is an inventor based in Santa Clara, California, and is associated with Applied Materials, Inc. His patent work addresses plasma control in semiconductor processing chambers.

Latest Patents

The supplied information lists one patent for Chin: “Chamber Impedance Management in a Processing Chamber.” The invention describes methods and apparatus for improving plasma uniformity by controlling plasma density over the center and circumferential edge regions of a substrate. It uses RF tuning circuits coupled to electrodes positioned relative to the substrate. Adjusting the circuits’ electrical characteristics can influence how the fundamental RF frequency and its harmonics affect processing. The approach provides separate controls for factors such as reactive neutral species concentration, ion energy and angular distribution, ion directionality, ion flux, and uniformity across the substrate surface.

Career Highlights

Chin’s listed patent reflects work on managing chamber impedance and tuning plasma conditions during substrate processing. The supplied information identifies Applied Materials, Inc. as his company.

Collaborations

The supplied information names Linying Cui and James Rogers as Chin’s coworkers. Their specific contributions to the patent are not provided.

Conclusion

William Chin’s listed invention focuses on using RF tuning to improve plasma uniformity and control processing conditions across a substrate, representing a contribution to semiconductor manufacturing technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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