Stafford, TX, United States of America

William C Waldrop

This inventor holds 1 USPTO granted patent. Top assignee: Texas Instruments Corporation. Active years: 2001.

IDiyas Innovation Intelligence. (2026). Inventor Profile: William C Waldrop. Retrieved from https://idiyas.com/inventor/william-c-waldrop

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 5(Granted Patents)


Company Filing History:


Years Active: 2001

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1 patent (USPTO):Explore Patents

Title: William C. Waldrop and Clock Input Noise Suppression

Introduction

William C. Waldrop is an inventor associated with Stafford, Texas, and Texas Instruments Corporation. His recorded patent concerns clock circuitry designed to suppress noise and provide clock pulses with a predetermined width. Waldrop is credited with 1 patent in the information provided.

Latest Patents

The listed patent, “Clock Input Buffer with Noise Suppression,” describes a circuit that receives a clock input signal and a control signal. A delay circuit produces a clock control signal at different times depending on the control signal’s logic state. That control signal enables a clock circuit, which generates pulses of a predetermined width in response to transitions of the clock input. The design addresses noise suppression in clock-input circuitry.

Career Highlights

Waldrop’s listed invention reflects work on digital circuit design and clock-signal management. The available information associates him with Texas Instruments Corporation but does not specify his role, employment dates, or other career details.

Collaborations

Jason M. Brown and Daniel B. Penney are identified as Waldrop’s coworkers. The information provided does not establish whether they collaborated with him on the listed patent.

Conclusion

William C. Waldrop’s recorded patent highlights an approach to managing clock signals through delayed control and fixed-width pulses, with the aim of suppressing noise in clock-input circuitry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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