Hillsboro, OR, United States of America

William Anderson, Jr

This inventor holds 1 USPTO granted patent. Top assignee: Computervision Corporation. Active years: 1994.

IDiyas Innovation Intelligence. (2026). Inventor Profile: William Anderson, Jr. Retrieved from https://idiyas.com/inventor/william-anderson-jr

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 31(Granted Patents)


Company Filing History:


Years Active: 1994

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1 patent (USPTO):Explore Patents

Title: The Innovations of William Anderson, Jr.

Introduction

William Anderson, Jr. is an accomplished inventor based in Hillsboro, OR (US). He has made significant contributions to the field of electronic design through his innovative patent. His work focuses on enhancing the efficiency of computer-aided design tools, which are essential for modern electronic circuitry.

Latest Patents

William Anderson, Jr. holds a patent for a "Method and apparatus for deferred package assignment for components." This invention allows users to generate a design implementation for electronic circuitry without the immediate need for packaging information. The system provides a packaging tool that can be utilized after the design schematic has been completed and verified. This flexibility enables users to focus on the functional aspects of their designs before addressing packaging requirements.

Career Highlights

Anderson is associated with Computervision Corporation, where he has applied his expertise in electronic design. His role at the company has allowed him to collaborate with other talented professionals in the field. His coworker, Mark D Pease, has also contributed to various projects within the organization.

Collaborations

Due to space constraints, the details of collaborations will not be included.

Conclusion

William Anderson, Jr. is a notable inventor whose work has advanced the capabilities of computer-aided design tools in electronic circuitry. His innovative approach to deferred packaging has the potential to streamline the design process for engineers and designers alike.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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