Hsinchu, Taiwan

Wen-Chung Fang

This inventor holds 1 USPTO granted patent. Top assignee: Apex Design Systems, Inc.. Active years: 2007.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Wen-Chung Fang. Retrieved from https://idiyas.com/inventor/wen-chung-fang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 13(Granted Patents)


Company Filing History:


Years Active: 2007

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1 patent (USPTO):Explore Patents

Title: Innovations of Wen-Chung Fang in Electronic Design Automation

Introduction

Wen-Chung Fang is a notable inventor based in Hsin-Chu, Taiwan. He has made significant contributions to the field of Electronic Design Automation (EDA). His innovative work focuses on improving circuit layout efficiency and reducing chip size.

Latest Patents

Wen-Chung Fang holds a patent titled "Chip-area reduction and congestion alleviation by timing-and-routability-driven empty-space propagation." This EDA process is designed to collect and relocate empty spaces among cells on a circuit layout. The goal is to utilize these spaces for productive purposes, such as reducing chip size and alleviating routability congestion. The process involves globally moving empty spaces to target areas, followed by local refinement.

Career Highlights

Wen-Chung Fang is currently employed at Apex Design Systems, Inc. His work at the company has been instrumental in advancing EDA technologies. He has demonstrated a strong commitment to innovation and efficiency in circuit design.

Collaborations

Wen-Chung Fang collaborates with Tsu-Wei Ku, a talented woman in the field. Their partnership has contributed to the development of cutting-edge solutions in EDA.

Conclusion

Wen-Chung Fang's contributions to Electronic Design Automation exemplify the impact of innovative thinking in technology. His patent and work at Apex Design Systems, Inc. highlight his dedication to enhancing circuit design efficiency.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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