Webster B Meier

Title: The Innovations of Webster B. Meier

Introduction

Webster B. Meier is a notable inventor based in Palo Alto, CA (US). He has made significant contributions to the field of technology, particularly in the area of dynamic random-access memory (DRAM) systems. His innovative approach has led to advancements that enhance the efficiency and performance of memory devices.

Latest Patents

One of Webster B. Meier's key patents is titled "Staggered refresh for DRAM array." This invention introduces a method where each successive refresh to the multiple banks of a DRAM array is staggered by one clock period. For instance, at a frequency of 10 MHz, the time required to refresh one row in each DRAM of each bank is approximately 0.7 microseconds, which constitutes about 4.4% of the total allowable maximum time between refresh cycles. This staggered refresh technique effectively avoids large power supply current spikes while minimizing the impact on memory access bandwidth. He holds 1 patent related to this innovative technology.

Career Highlights

Webster B. Meier has had a distinguished career, working at National Semiconductor Corporation, where he has been able to apply his expertise in memory technology. His work has contributed to the development of more efficient memory systems that are crucial for modern computing.

Collaborations

Throughout his career, Webster has collaborated with several talented individuals, including Farid A. Yazdy and Richard Dean Henderson. These collaborations have fostered an environment of innovation and have led to advancements in the field of semiconductor technology.

Conclusion

Webster B. Meier's contributions to the field of DRAM technology exemplify the impact of innovative thinking in the tech industry. His patent on staggered refresh techniques showcases his commitment to enhancing memory performance and efficiency.