Kozhikode, India

Vysakh Kolassery

This inventor holds 1 USPTO granted patent. Top assignee: International Business Machines Corporation. Active years: 2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Vysakh Kolassery. Retrieved from https://idiyas.com/inventor/vysakh-kolassery

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2016

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1 patent (USPTO):Explore Patents

Title: Vysakh Kolassery: Innovator in Memory Debugging Techniques

Introduction

Vysakh Kolassery is a notable inventor based in Kozhikode, India. He has made significant contributions to the field of memory debugging, particularly in post-silicon validation processes. His innovative approach addresses critical challenges in ensuring the reliability of memory systems.

Latest Patents

Vysakh Kolassery holds a patent titled "Efficient debugging of memory miscompare failures in post-silicon validation." This patent focuses on debugging techniques that utilize data from both the post-silicon and pre-silicon phases. The method involves several steps, including receiving a first memory location that experiences a miscompare, backtracking through instructions to identify dependent locations, and comparing simulation values with actual values to determine the cause of the miscompare.

Career Highlights

Vysakh Kolassery is currently employed at International Business Machines Corporation (IBM). His work at IBM has allowed him to develop and refine his innovative debugging techniques, contributing to advancements in memory validation processes.

Collaborations

Vysakh collaborates with talented professionals in his field, including Gunaranjan Kurucheti and Subrat K Panda. These collaborations enhance the development of innovative solutions in memory debugging.

Conclusion

Vysakh Kolassery is a pioneering inventor whose work in memory debugging techniques has the potential to significantly impact the field of post-silicon validation. His contributions reflect a commitment to innovation and excellence in technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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