Roznov pod Radhostem, Czechia

Vit Janirek

This inventor holds 1 USPTO granted patent. Top assignee: Semiconductor Components Industries, LLC. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Vit Janirek. Retrieved from https://idiyas.com/inventor/vit-janirek

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 1.0

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Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Vit Janirek and Semiconductor Manufacturing Innovation.

Introduction

Vit Janirek is an inventor based in Rožnov pod Radhoštěm, Czech Republic. His patent work concerns semiconductor manufacturing and methods for improving the quality of CZ silicon substrates.

Latest Patents

Janirek is associated with 1 patent, titled “Methods of Manufacturing Semiconductor Devices and Semiconductor Devices.” The invention describes a process that first anneals an unpolished CZ silicon substrate in an inert environment and then anneals it in a wet oxidation environment. The first step dissolves oxide along the inner walls of voids in the substrate, while the second helps fill those voids with semiconductor interstitials.

In some examples, the CZ silicon is grown from an ingot using a magnetic field and continuous counter-doping. The process is intended to reduce crystal-originated particle defects and oxygen concentration, while also reducing radial resistivity variation.

Career Highlights

Janirek’s listed company affiliation is Semiconductor Components Industries, LLC. His patent reflects work on silicon substrate processing and semiconductor device manufacturing.

Collaborations

The provided information names David Lysacek and Jan Hybl as Janirek’s coworkers. It does not specify their roles in the patent or describe particular collaborative contributions.

Conclusion

Vit Janirek’s patent focuses on annealing techniques designed to improve CZ silicon substrate properties and support semiconductor device manufacturing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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