Bengaluru, India

Viresh Chinchansure

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Texas Instruments Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Viresh Chinchansure. Retrieved from https://idiyas.com/inventor/viresh-chinchansure

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Viresh Chinchansure: Integrated-Circuit Capacitor Innovation.

Introduction

Viresh Chinchansure is an inventor based in Bengaluru, India. His patent work includes an integrated-circuit capacitor design that arranges metal lines across two levels.

Latest Patents

The provided information lists one patent for Chinchansure: “MIM Flux Capacitor with Thin and Thick Metal Levels.” The invention describes an integrated circuit with first and second metal levels above a semiconductor substrate. In the first level, lines belonging to two capacitor electrodes alternate with one another. In the second level, two additional sets of parallel lines form further capacitor electrodes, positioned over selected lines in the first level. This arrangement describes a metal-insulator-metal capacitor structure using thin and thick metal levels.

Career Highlights

Chinchansure is associated with Texas Instruments Incorporated. His listed patent reflects work on capacitor structures integrated into semiconductor devices. The supplied information identifies 1 patent.

Collaborations

Kumar Anurag Shrivastava is identified as Chinchansure’s coworker. The information provided does not specify whether Shrivastava collaborated on the listed patent.

Conclusion

Viresh Chinchansure’s listed invention focuses on arranging capacitor electrodes across multiple metal levels in an integrated circuit, highlighting his contribution to semiconductor design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…