Vinay Vashishtha

Title: Vinay Vashishtha: Innovator in Sequential State Elements

Introduction

Vinay Vashishtha is a notable inventor based in Tempe, AZ (US). He has made significant contributions to the field of logic design, particularly in the area of self-correcting systems. His innovative work has led to the development of a unique patent that enhances the efficiency of sequential state elements.

Latest Patents

Vinay Vashishtha holds a patent titled "Muller C-element as majority gate for self-correcting triple modular redundant logic with low-overhead modes." This patent describes embodiments of a sequential state element (SSE) capable of providing triple modular redundant (TMR) correction. The SSE features a setup stage that generates an output bit signal while a clock signal is in the first clock state. Additionally, it produces a feedback input bit signal based on the output bit state. Notably, the feedback stage can provide TMR correction without relying on this feedback signal, utilizing two other feedback input bit signals from different SSEs instead. This innovative approach reduces the power and area consumed by the SSE.

Career Highlights

Vinay Vashishtha is affiliated with Arizona State University, where he continues to advance his research and development in logic design. His work is characterized by a commitment to improving the efficiency and reliability of electronic systems.

Collaborations

Vinay has collaborated with esteemed colleagues such as Srivatsan Chellappa and Lawrence T Clark. Their combined expertise contributes to the innovative research environment at Arizona State University.

Conclusion

Vinay Vashishtha's contributions to the field of logic design through his patent and collaborative efforts highlight his role as an influential inventor. His work not only advances technology but also sets a foundation for future innovations in self-correcting systems.