Vidyasagar Ganesan

Title: The Innovative Mind of Vidyasagar Ganesan

Introduction

Vidyasagar Ganesan is a notable inventor based in Santa Clara, CA. He has made significant contributions to the field of processor design, particularly in power modeling methodologies. His work has implications for improving the efficiency and performance of pipelined processors.

Latest Patents

Vidyasagar holds a patent for a "Power modeling methodology for a pipelined processor." This innovative method models the power behavior of a pipelined processor by integrating a power model into a cycle-accurate simulator. The process involves dividing the design blocks of the processor into sub-blocks and developing power modeling equations for each sub-block. These equations are created through collaboration between the sub-block circuit designer and the simulator developer, utilizing relevant activity information available in the simulator model. The equations are calculated multiple times with varying power parameters to represent different power conditions. Ultimately, the sub-block power is summed during each simulation cycle to generate full-chip power for multiple power conditions.

Career Highlights

Vidyasagar has had a successful career at Sun Microsystems, Inc., where he has applied his expertise in processor design and power modeling. His innovative approach has contributed to advancements in the efficiency of computing technologies.

Collaborations

Throughout his career, Vidyasagar has collaborated with talented individuals such as Miriam G. Blatt and Poonacha P. Kongetira. These collaborations have fostered a creative environment that has led to significant advancements in their respective fields.

Conclusion

Vidyasagar Ganesan's contributions to power modeling methodologies for pipelined processors highlight his innovative spirit and dedication to advancing technology. His work continues to influence the design and efficiency of modern processors.