The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2005
Filed:
Dec. 07, 2001
Miriam G. Blatt, Menlo Park, CA (US);
Poonacha Kongetira, Menlo Park, CA (US);
David J. Greenhill, Portola Valley, CA (US);
Vidyasagar Ganesan, Santa Clara, CA (US);
Miriam G. Blatt, Menlo Park, CA (US);
Poonacha Kongetira, Menlo Park, CA (US);
David J. Greenhill, Portola Valley, CA (US);
Vidyasagar Ganesan, Santa Clara, CA (US);
Sun Microsystems, Inc., Santa Clara, CA (US);
Abstract
A method for modeling the power behavior of a pipelined processor has been developed. The method uses a power model integrated into a cycle accurate simulator. To create the power model, design blocks of the processor are divided into sub-blocks. Power modeling equations for each sub-block are developed by collaboration between the sub-block circuit designer and the simulator developer, using activity information relevant to the sub-block that is available in the simulator model. Each equation is calculated multiple times with different sets of power parameters to represent varying power conditions. Every simulation cycle, sub-block power is summed to generate full-chip power for multiple power conditions.