Beaverton, OR, United States of America

Van H Lee

This inventor holds 2 USPTO granted patents. Top assignee: Intel Corporation. Active years: 2016-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Van H Lee. Retrieved from https://idiyas.com/inventor/van-h-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 4.8

ph-index = 1

Forward Citations = 19(Granted Patents)


Location History:

  • Portland, OR (US) (2016)
  • Beaverton, OR (US) (2022)

Company Filing History:


Years Active: 2016-2022

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2 patents (USPTO):Explore Patents

Title: Innovations of Van H Lee

Introduction

Van H Lee is a notable inventor based in Beaverton, OR (US). He has made significant contributions to the field of thin film transistors, holding 2 patents that showcase his innovative approach to semiconductor technology.

Latest Patents

His latest patents include advancements in vertical multi-gate thin film transistors. These transistors feature a gate electrode pillar clad with a gate dielectric, which is further clad with a semiconductor layer. The design allows for source or drain metallization to be embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. This configuration enables the biasing of the gate electrode to induce one or more transistor channels within the semiconductor layer, effectively coupling the source and drain metallization. The width of the channel is proportional to the height of the gate electrode pillar, while the length is proportional to the spacing between contacts occupied by the semiconductor layer. Additionally, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).

Another significant patent is for a non-planar gate all-around device and its method of fabrication. This device includes a substrate with a top surface featuring a first lattice constant. Embedded epi source and drain regions are formed on this surface, having a second lattice constant that differs from the first. Channel nanowires with a third lattice constant are formed between the embedded regions. The design includes a bottom-most channel nanowire with a bottom gate isolation formed on the substrate surface beneath it. A gate dielectric layer surrounds each channel nanowire, topped with a gate electrode.

Career Highlights

Van H Lee is currently employed at Intel Corporation, where he continues to push the boundaries of semiconductor technology. His work has been instrumental in developing advanced transistor designs that enhance performance and efficiency.

Collaborations

He has collaborated with notable coworkers such as Willy Rachmady and Ravi Pillarisetty, contributing to a dynamic and innovative work environment.

Conclusion

Van H Lee's contributions to the field of thin film transistors and semiconductor technology highlight his role as a leading inventor. His patents reflect a commitment to innovation and advancement in the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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