Tung S Chang

Title: Innovations by Tung S Chang in CMOS Integrated Circuits

Introduction

Tung S Chang is a notable inventor based in Santa Clara County, CA. He has made significant contributions to the field of semiconductor technology, particularly in the area of complementary metal oxide semiconductor (CMOS) integrated circuits. His work has led to advancements that enhance the performance and reliability of these essential components in modern electronics.

Latest Patents

Tung S Chang holds a patent for the "Reduction of contact resistance in CMOS integrated circuit chips." This patent presents a process for forming openings, or vias, in the glass layer of CMOS integrated circuit chips. The method involves applying a pattern of openings to the glass layer using conventional resist/mask techniques. A plasma is utilized to remove the glass and any silicon dioxide layer, exposing portions of the N+ and P+ circuit elements. The process addresses the decreased conductivity of the crystalline lattice structure of the N+ material, which is caused by plasma exposure. This added resistance is mitigated to acceptable levels before the metallization layer is applied by placing the chip in an inert gas atmosphere at an appropriate elevated temperature for a specified duration.

Career Highlights

Tung S Chang has had a successful career in the semiconductor industry, working with Storage Technology Partners. His expertise in CMOS technology has positioned him as a valuable asset in the development of innovative solutions that improve circuit performance.

Collaborations

Tung S Chang has collaborated with his coworker, Jenq S Chang, to further advance their research and development efforts in the field of integrated circuits.

Conclusion

Tung S Chang's contributions to the field of CMOS integrated circuits demonstrate his commitment to innovation and excellence in semiconductor technology. His patent reflects a significant advancement that addresses critical challenges in the industry.