This inventor holds 1 USPTO granted patent. Top assignee: Fujitsu Corporation. Active years: 2008.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2008
Title: Tsutomu Terazawa: Data Buffer Circuit Inventor
Introduction
Tsutomu Terazawa is an inventor associated with Kasugai, Japan, and Fujitsu Corporation. His patent work includes a data buffer circuit designed to support data transfer between synchronous and asynchronous systems.
Latest Patents
Terazawa is credited with 1 patent: “Data Buffer Circuit, Interface Circuit and Control Method Therefor.” The invention describes a buffer that transfers data between a synchronous circuit and an asynchronous circuit, as well as an interface for controlling transfers between a synchronous memory circuit and an asynchronous circuit.
In one implementation, the buffer sits between an image processing system and a main system. It includes a one-port RAM, a control signal generating section, a subsequent-cycle address generating section, and a selector. The selector supplies the current-cycle address for a write access and the subsequent-cycle address for a read access.
Career Highlights
Terazawa’s listed patent is associated with Fujitsu Corporation. It addresses circuit design and control methods for managing data transfers across systems with different timing characteristics.
Collaborations
His listed coworkers include Hiromichi Mizuno and Toshiyuki Nishii.
Conclusion
Tsutomu Terazawa’s patent describes a practical approach to buffering and controlling data transfers between synchronous and asynchronous circuits.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile