Yokosuka, Japan

Toshirou Shinohara

This inventor holds 1 USPTO granted patent. Top assignee: Nissan Motor Company Limited. Active years: 1998.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Toshirou Shinohara. Retrieved from https://idiyas.com/inventor/toshirou-shinohara

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 17(Granted Patents)


Company Filing History:


Years Active: 1998

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1 patent (USPTO):Explore Patents

Title: Toshirou Shinohara: Semiconductor Chip Damage Detection

Introduction

Toshirou Shinohara is an inventor associated with Yokosuka, Japan, and Nissan Motor Company Limited. His patent work includes a circuit designed to detect physical damage in semiconductor chips while they are operating.

Latest Patents

Shinohara is associated with 1 patent, titled “Chip Damage Detecting Circuit for Semiconductor IC.” The invention describes a chip-check circuit that runs from an input terminal to an output terminal and scans a predetermined area of a semiconductor integrated circuit. Its signal line passes near or through a circuit block so that damage to the block can also break the line, helping reveal cracks and other defects during operation. The design may also include inverters or two-wire logic circuits.

Career Highlights

Shinohara’s documented patent contribution focuses on semiconductor reliability and on detecting chip defects during operation. His association with Nissan Motor Company Limited connects his work to an organization active in automotive technology.

Collaborations

Noriyuki Abe and Toshimi Abo are identified as Shinohara’s coworkers. The available information does not specify their roles in the patent or whether they collaborated on the invention.

Conclusion

Toshirou Shinohara’s patent describes a practical approach to identifying semiconductor chip damage by monitoring a circuit designed to fail when nearby chip structures are damaged.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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