Chantilly, VA, United States of America

Tirumale Ramesh

This inventor holds 1 USPTO granted patent. Top assignee: Jackson State University. Active years: 2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tirumale Ramesh. Retrieved from https://idiyas.com/inventor/tirumale-ramesh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1


Company Filing History:


Years Active: 2022

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1 patent (USPTO):Explore Patents

Title: The Innovative Mind of Tirumale Ramesh

Introduction

Tirumale Ramesh is a notable inventor based in Chantilly, VA (US). He has made significant contributions to the field of computing architectures. His work focuses on enhancing the efficiency and performance of multi-purpose and heterogeneous computing systems.

Latest Patents

Ramesh holds a patent for a "Dynamic reconfigurable multi-level cache for multi-purpose and heterogeneous computing architectures." This innovative system includes a plurality of processors and memory modules executed by these processors. The dynamic reconfigurable cache comprises a multi-level cache that implements a combination of L1, L2, and L3 caches. These caches can be dynamically reconfigured to various sizes based on the application data size associated with the application being executed. The system also features a reconfiguration control and distribution module that performs dynamic reconfiguration based on the application data size.

Career Highlights

Tirumale Ramesh is currently associated with Jackson State University, where he continues to contribute to research and development in computing technologies. His work has implications for improving the performance of computing systems across various applications.

Collaborations

Ramesh collaborates with Khalid Abed, working together to advance their research and innovations in the field of computing.

Conclusion

Tirumale Ramesh's contributions to dynamic reconfigurable cache systems highlight his innovative spirit and dedication to enhancing computing architectures. His work continues to influence the future of technology in significant ways.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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