Tick Sern Loh

Title: Innovations of Tick Sern Loh

Introduction

Tick Sern Loh is an accomplished inventor based in Santa Clara, CA. He has made significant contributions to the field of integrated circuits, particularly in improving the performance and reliability of memory interface signals. His innovative approach addresses critical challenges in transistor aging, which is essential for maintaining optimal timing margins.

Latest Patents

One of Tick Sern Loh's notable patents is titled "Methods for mitigating transistor aging to improve timing margins for memory interface signals." This patent describes an integrated circuit that communicates with external components. The integrated circuit includes driver circuits that output clock signals and associated control signals according to a predetermined interface protocol. To mitigate potential transistor aging effects, the control signals are periodically toggled even during idle periods, enhancing timing margins.

Career Highlights

Tick Sern Loh is currently employed at Intel Corporation, a leading technology company known for its advancements in semiconductor manufacturing. His work at Intel has allowed him to focus on innovative solutions that improve the performance of integrated circuits.

Collaborations

Throughout his career, Tick Sern Loh has collaborated with talented individuals such as Tat Hin Tan and Chee Hak Teh. These collaborations have fostered a creative environment that encourages the development of groundbreaking technologies.

Conclusion

Tick Sern Loh's contributions to the field of integrated circuits exemplify the importance of innovation in technology. His work not only addresses current challenges but also paves the way for future advancements in memory interface signals.