Tatia E Butts

Title: Tatia E. Butts: Integrated Circuit Design Innovation.

Introduction

Tatia E. Butts is an inventor associated with Manassas, Virginia, and BAE Systems Information and Electronic Systems Integration Inc. Her patent work addresses a practical challenge in integrated circuit design: placing fill patterns while preserving areas where such patterns are not permitted.

Latest Patents

Butts is credited with 1 patent, titled “Method for Providing a Fill Pattern for an Integrated Circuit Design.” The invention describes generating a keepout file from chip layout data to map areas where fill patterns cannot be placed. That map is overlaid with a fill pattern, and pattern elements that overlap keepout areas are removed to create a final-fill file. The resulting fill data is then incorporated into the chip layout, after which the design is checked for design-rule integrity and logical-to-physical correspondence.

Career Highlights

The patent reflects work at the intersection of semiconductor layout and design verification. By coordinating fill-pattern placement with keepout data and subsequent integrity checks, the method provides a structured approach to incorporating fill into an integrated circuit design.

Collaborations

Butts is associated with BAE Systems Information and Electronic Systems Integration Inc. Her listed coworkers include Charles N. Alcorn and Arnett J. Brown III.

Conclusion

Tatia E. Butts’s patented method focuses on integrating fill patterns into chip layouts while respecting restricted areas and verifying the completed design.