Yokohama, Japan

Tarou Iwashiro

This inventor holds 3 USPTO granted patents and 1 published patent application. Top assignee: Kabushiki Kaisha Toshiba. Active years: 2013-2016.

USPTO Granted Patents = 3 

% Patents Active = 100.0

Average Co-Inventor Count = 2.6

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2013-2016

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3 patents (USPTO):Explore Patents

Title: Tarou Iwashiro: Innovator in Semiconductor Memory Technology

Introduction

Tarou Iwashiro is a prominent inventor based in Yokohama, Japan. He has made significant contributions to the field of semiconductor memory technology. With a total of 3 patents to his name, Iwashiro continues to push the boundaries of innovation in this critical area.

Latest Patents

Iwashiro's latest patents include a nonvolatile semiconductor memory system that features improved error correction capabilities. According to one embodiment, this memory system comprises a memory cell array, a first error correction part, a second error correction part, and a third error correction part. The memory cell array includes a first storage area where 1-bit data is stored in one memory cell, and a second storage area where data of multiple bits is stored in one memory cell. When data is written to the first storage area, the first error correction part generates first parity data in the row direction based on the data. The second error correction part is responsible for correcting errors in the data using the first parity data read from the memory cell array. Additionally, the third error correction part generates second parity data in the column direction based on data from multiple pages.

Another notable patent involves a memory device that includes a semiconductor memory and a controller that manages the semiconductor memory. The controller consists of a first command issuing module, a second command issuing module, an error correction module, and a control module. The first command issuing module issues a read command to the semiconductor memory, while the second command issuing module issues a command that does not involve reading data from the semiconductor memory. The error correction module is designed to correct any errors in the data supplied from the semiconductor memory, and the control module oversees the operation of the error correction module and the command issuing modules.

Career Highlights

Tarou Iwashiro is currently employed at Kabushiki Kaisha Toshiba, a leading company in the technology sector. His work at Toshiba has allowed him to develop innovative solutions that enhance the performance and reliability of semiconductor memory systems.

Collaborations

Iwashiro has collaborated with notable colleagues such as Yoshihisa Kondo and Masaru Ogawa. Their combined expertise has contributed to advancements in semiconductor technology.

Conclusion

Tarou Iwashiro is a key figure in the field of semiconductor memory technology, with a focus on improving error

Profile summary based on public USPTO records.
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