Worcester, MA, United States of America

Tahoura Mosavirik

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Worcester Polytechnic Institute. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tahoura Mosavirik. Retrieved from https://idiyas.com/inventor/tahoura-mosavirik

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Tahoura Mosavirik and Electronic Tampering Detection.

Introduction

Tahoura Mosavirik is an inventor associated with Worcester Polytechnic Institute in Worcester, Massachusetts. His patent work addresses the detection of physical tampering with computing hardware.

Latest Patents

Mosavirik is credited with 1 patent, titled “Electronic Tampering Detection.” The invention describes a method for identifying physical attacks on a computing device by monitoring the frequency response of the power distribution network that supplies a circuit board. A sensor or field-programmable gate array gathers the response during operation and compares it with responses associated with known tampering events. The system uses that comparison to determine whether tampering has occurred.

Career Highlights

Mosavirik’s listed patent reflects work on hardware security and tamper detection. The approach uses changes in a circuit board’s electrical behavior as evidence that the device may have been physically attacked.

Collaborations

His listed coworkers include Shahin Tajik and Patrick Schaumont. The patent’s focus on circuit-board monitoring and security aligns with collaborative research in computing hardware and protection against physical attacks.

Conclusion

Tahoura Mosavirik’s patent presents a method for detecting physical tampering by analyzing power-network frequency responses, contributing to research on the security of computing devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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