Seoul, South Korea

Tae W Yoo

This inventor holds 11 USPTO granted patents. Top assignees: Samsung Electronics Co., Ltd., Other. Active years: 1993-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tae W Yoo. Retrieved from https://idiyas.com/inventor/tae-w-yoo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 1.2

ph-index = 5

Forward Citations = 139(Granted Patents)


Location History:

  • Seocho-dong, Seocho-ku, Seoul, KR (1993 - 1994)
  • San Seocho-dong Seocho-Ku, Seoul, KR (1996)
  • Seocho-ku, Seoul, KR (1996)
  • Seoul, KR (1994 - 2024)

Company Filing History:

goldMedal3 out of 132,108 
 
Samsung Electronics Co., Ltd.
 patents
silverMedal3 out of 834,601 
Other
 patents
where one patent can have more than one assignee

Years Active: 1993-2025

Loading Chart...
11 patents (USPTO):Explore Patents

Title: Tae W. Yoo: Semiconductor Packaging Inventor

Introduction

Tae W. Yoo is an inventor based in Seoul, South Korea. His patent work includes semiconductor packaging, and he is associated with 11 patents.

Latest Patents

Yoo’s latest listed patent, “Semiconductor Package Having Pads with Stepped Structure,” describes a package containing three stacked semiconductor chips. A pad on the middle chip has a wider first portion and a narrower portion that protrudes vertically from it. A pad on the upper chip faces the first pad, with a solder ball surrounding the narrower portion between the two pads. This stepped arrangement addresses the connection between stacked chips.

Career Highlights

Yoo is associated with Samsung Electronics Co., Ltd. His patent portfolio includes work on semiconductor package structures and interconnections.

Collaborations

Yoo’s listed coworkers include Myung Kee Chung and Hyun Soo Chung.

Conclusion

Tae W. Yoo’s patent record highlights his contributions to semiconductor packaging, particularly structures for connecting stacked chips.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…