San Jose, CA, United States of America

Suketu Parikh

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Applied Materals, Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Suketu Parikh. Retrieved from https://idiyas.com/inventor/suketu-parikh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Suketu Parikh and Copper-Doped Hybrid Metallization

Introduction

Suketu Parikh is an inventor based in San Jose, California. His patent work addresses interconnect structures designed to reduce resistivity and improve dopant interfaces in semiconductor devices.

Latest Patents

Parikh is associated with 1 patent, titled “Structures with Copper Doped Hybrid Metallization for Line and Via.” The invention describes an interconnect opening with a tantalum nitride barrier and a cobalt or ruthenium liner. It uses a copper layer with a higher dopant content in the via’s lower portion and a second copper layer with a lower dopant content above it. The specified dopant content is approximately 0.5% to 10% in the first layer and more than zero to approximately 0.5% in the second layer. This layered approach is intended to provide low-resistivity interconnects and high-dopant interfaces.

Career Highlights

Parikh is associated with Applied Materials, Inc., a company working in materials engineering and semiconductor manufacturing technologies. His patent reflects work on the materials and structures used to form semiconductor lines and vias.

Collaborations

The provided information lists Alexander Jansen and Joung Joo Lee as Parikh’s coworkers. Their names are associated with his professional context, though specific roles in the patent are not stated here.

Conclusion

Suketu Parikh’s patent focuses on combining doped copper layers with barrier and liner materials to improve semiconductor interconnect structures.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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