Daejeon, South Korea

Suk Min Seo

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Korea Advanced Institute of Science and Technology. Active years: 2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Suk Min Seo. Retrieved from https://idiyas.com/inventor/suk-min-seo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 6(Granted Patents)


Company Filing History:


Years Active: 2017

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1 patent (USPTO):Explore Patents

Title: Suk Min Seo - Innovator in Chip Packaging Technology.

Introduction

Suk Min Seo is a prominent inventor based in Daejeon, South Korea. He has made significant contributions to the field of chip packaging technology. His innovative approach has led to the development of a unique method that enhances the efficiency and effectiveness of chip packaging.

Latest Patents

Suk Min Seo holds a patent for a "Chip packaging method and chip package using hydrophobic surface." This method involves creating superhydrophobic surfaces and hydrophilic surfaces on specific areas of chips or boards. The process generates liquid metal balls on these hydrophilic surfaces, which are then combined to package the chips effectively.

Career Highlights

Suk Min Seo is affiliated with the Korea Advanced Institute of Science and Technology. His work has been instrumental in advancing chip packaging techniques, making them more reliable and efficient. His innovative methods are paving the way for future developments in the semiconductor industry.

Collaborations

Suk Min Seo has collaborated with notable colleagues, including Jong Hun Kim and Hyo Hoon Park. Their combined expertise has contributed to the success of their projects and innovations in chip packaging technology.

Conclusion

Suk Min Seo's contributions to chip packaging technology demonstrate his commitment to innovation and excellence. His patented methods are set to influence the future of the semiconductor industry significantly.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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