San Jose, CA, United States of America

Steven C Steps

This inventor holds 3 USPTO granted patents. Top assignee: Hewlett-Packard Company. Active years: 1987-1989.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Steven C Steps. Retrieved from https://idiyas.com/inventor/steven-c-steps-jo8udw1y

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 1.2

ph-index = 3

Forward Citations = 102(Granted Patents)


Company Filing History:


Years Active: 1987-1989

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3 patents (USPTO):Explore Patents

Title: Steven C Steps: Innovator in Cache Memory Systems

Introduction

Steven C Steps is a notable inventor based in San Jose, CA. He has made significant contributions to the field of computer systems, particularly in cache memory architecture. With a total of 3 patents, his work has advanced the efficiency and performance of computing systems.

Latest Patents

One of his latest patents is a write-back cache system using concurrent address transfers to setup. This innovative computer system allows only the cache memory to communicate with the main memory. The same address used in the cache is sent simultaneously to the main memory. This design enables the main memory RAMs to be read to the cache without delays caused by the main memory address setup time. Additionally, since the main memory is only accessible through the cache memory, there are no delays from other system modules, such as the I/O controller. The contents of the cache memory are written into a temporary register before being sent to the main memory, allowing for a main memory read to occur before the cache write-back. This results in a significant reduction in the overhead time typically associated with cache memories.

Another patent by Steven C Steps is focused on odd/even storage in cache memory. This architecture features a two-block wide cache memory made up of a map RAM and two cache data RAMs, each one word wide. The selection system allows data to be chosen from either one or both cache data RAMs, depending on whether the access is between the cache and CPU or between the cache and main memory. The data stored in the two cache data RAMs has a specific address configuration, optimizing the storage of even and odd addresses.

Career Highlights

Steven C Steps has had a distinguished career at Hewlett-Packard Company, where he has been instrumental in developing innovative technologies. His expertise in cache memory systems has positioned him as a key figure in the advancement of computer architecture.

Collaborations

He has collaborated with various professionals in the field, including his coworker, James S Finnell. Their combined efforts have contributed to the successful development of cutting-edge technologies in computing.

Conclusion

Steven C Steps is a prominent inventor whose work in cache memory systems has significantly impacted the field of computer technology. His innovative patents continue to influence the efficiency of computing systems today.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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