This inventor holds 1 USPTO granted patent. Top assignee: Silicon Graphics, Incorporated. Active years: 1996.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 1996
Title: The Innovations of Steve Ciavagia
Introduction
Steve Ciavagia is an accomplished inventor based in Williston, Vermont. He has made significant contributions to the field of computer systems, particularly in the area of cache management. His innovative approach has led to the development of a unique patent that addresses critical issues in multi-processor environments.
Latest Patents
Ciavagia holds a patent for a "System and method for controlling split-level caches." This invention provides a method for preventing data loss and deadlock in a multi-processor computer system. The system includes a split-level cache with a byte-writable first level and a word-writable second level. The method involves monitoring the second level cache to determine if a forced atomic (FA) instruction is present in the pipeline. By delaying interventions to the second level cache until the FA instruction exits the pipeline, the method ensures that data written by cache memory access instructions is not destroyed. Additionally, it monitors for possible miss (PM) instructions to prevent deadlock between processing units.
Career Highlights
Steve Ciavagia is currently employed at Silicon Graphics, Incorporated, where he continues to innovate in the field of computer technology. His work has been instrumental in enhancing the efficiency and reliability of multi-processor systems. With a total of 1 patent, Ciavagia's contributions are noteworthy in the tech industry.
Collaborations
Throughout his career, Ciavagia has collaborated with notable colleagues, including Joseph P. Bratt and John Brennan. These partnerships have fostered an environment of innovation and creativity, leading to advancements in technology.
Conclusion
Steve Ciavagia's work exemplifies the spirit of innovation in the tech industry. His patent for controlling split-level caches addresses significant challenges in multi-processor systems, showcasing his expertise and commitment to advancing technology.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile