IDiyas

For the Inventor, By the Inventor

Ft. Collins, CO, United States of America

Stephen R Undy

USPTO Granted Patents = 18

Average Co-Inventor Count = 2.9

ph-index = 9

Forward Citations = 245(Granted Patents)


Location History:

  • Ft. Collins, CO (US) (2002 - 2004)
  • Fort Collins, CO (US) (1998 - 2005)
  • Ft Collins, CO (US) (2003 - 2008)

Company Filing History:

goldMedal11 out of 27,394 
 
Hewlett-packard Development Company, L.p.
 patents
silverMedal7 out of 9,638 
 
Hewlett-packard Company
 patents

Years Active: 1998-2008

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18 patents (USPTO):Explore Patents
1. 7356674 - Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine (2008-04-08),
2. 7343479 - Method and apparatus for implementing two architectures in a chip (2008-03-11),
3. 6944751 - Register renaming to reduce bypass and increase apparent physical register size (2005-09-13),
4. 6883150 - Automatic manufacturing test case generation method and system (2005-04-19),
5. 6799263 - Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted (2004-09-28),
6. 6721875 - Method and apparatus for implementing a single-syllable IP-relative branch instruction and a long IP-relative branch instruction in a processor which fetches instructions in bundle form (2004-04-13),
7. 6711671 - Non-speculative instruction fetch in speculative processing (2004-03-23),
8. 6678817 - Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine (2004-01-13),
9. 6647487 - Apparatus and method for shift register rate control of microprocessor instruction prefetches (2003-11-11),
10. 6629167 - Pipeline decoupling buffer for handling early data and late data (2003-09-30),
11. 6618801 - Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information (2003-09-09),
12. 6516388 - Method and apparatus for reducing cache pollution (2003-02-04),
13. 6493792 - Mechanism for broadside reads of CAM structures (2002-12-10),
14. 5961655 - Opportunistic use of pre-corrected data to improve processor performance (1999-10-05),
15. 5860097 - Associative cache memory with improved hit time (1999-01-12),
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