Stephen O'Kane

Title: Stephen O’Kane and an Area-Efficient On-Chip Timeout Generator

Introduction

Stephen O’Kane is an inventor associated with Greenock, Great Britain, and National Semiconductor Corporation. His recorded patent work concerns an integrated timeout circuit designed to provide reliable delays while minimizing area, power requirements, and sensitivity to temperature and supply voltage.

Latest Patents

The available information lists 1 patent for O’Kane: “Area Efficient On-Chip Timeout Generator with Low Temperature and Low Supply Voltage Dependency.” The invention describes a fully integrated BiCMOS analog time-delay circuit capable of generating delays of up to two milliseconds.

The circuit uses an ultralow PTAT current source and medium-value resistors to discharge an on-chip capacitor from a fixed, zero-temperature-coefficient voltage. A comparator monitors the capacitor and switches its output when the capacitor voltage falls below a reference voltage with a defined negative temperature coefficient. By coordinating the temperature characteristics of the reference-voltage generator and PTAT current source, the design makes the timeout period approximately independent of temperature to first order. The generated delay is also designed to remain independent of supply voltage and to operate with supplies as low as two volts.

Career Highlights

O’Kane’s listed patent reflects work on practical analog circuit design, particularly low-power timing functions for integrated systems. Its focus on compact implementation and stable operation under low-voltage conditions addresses constraints relevant to on-chip timeout circuits.

Collaborations

The supplied information identifies Andre Schouten as O’Kane’s coworker. Both are associated in the provided data with National Semiconductor Corporation.

Conclusion

Stephen O’Kane’s recorded invention presents an area-efficient, low-power timeout generator designed to maintain dependable timing across changes in temperature and supply voltage.