Salinas, CA, United States of America

Stanislav Mekhanoshin

This inventor holds 1 USPTO granted patent. Top assignees: Advanced Micro Devices Corporation, Ati Technologies Ulc. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Stanislav Mekhanoshin. Retrieved from https://idiyas.com/inventor/stanislav-mekhanoshin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Stanislav Mekhanoshin and Parallel Processor Memory Access

Introduction

Stanislav Mekhanoshin is an inventor associated with Salinas, California, and work at ATI Technologies ULC and Advanced Micro Devices Corporation. His patent concerns techniques for extending memory access in parallel processors.

Latest Patents

Mekhanoshin is credited with 1 patent: “Systems and Methods for Providing Extended Memory Access in a Parallel Processor.” The invention describes assigning data to shared memory or memories associated with multiple compute units, then scheduling the threads that use that data across those units. It also describes using separate instructions for the upper and lower bits of a memory address, with mode-setting commands controlling how those bits are combined. This approach enables processors to specify addresses wider than the address field of a single instruction can represent.

Career Highlights

Mekhanoshin’s listed company affiliations include ATI Technologies ULC and Advanced Micro Devices Corporation. His patent reflects work on memory addressing and task coordination in parallel-processing systems.

Collaborations

A listed coworker is Ahmed Mohammed Elshafiey Mohammed Eltantawy. The available information identifies this professional connection but does not specify their particular projects or contributions together.

Conclusion

Stanislav Mekhanoshin’s patent documents a method for extending address representation and coordinating memory use across parallel compute units.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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