Shuo-Wei Chen

Title: Innovations of Shuo-Wei Chen

Introduction

Shuo-Wei Chen is a notable inventor based in Santa Clara, CA. He has made significant contributions to the field of digital phase-locked loops (PLLs) with a focus on fractional and integer architectures. With a total of 2 patents, his work has advanced the technology used in frequency generation and counting.

Latest Patents

One of Shuo-Wei Chen's latest patents involves the development of fractional and integer PLL architectures. This digital fractional PLL introduces an accumulated phase offset before the digital voltage-controlled oscillator (VCO) to achieve the fractional part of the division ratio. The digital accumulator integrates a fractional component, allowing the PLL to function as an integer-N PLL when the fractional component is set to zero. Additionally, a de-skew timing configuration is utilized to eliminate any time mismatch between the integer and fractional counters of the PLL. This innovation merges the functions of frequency generation and fractional frequency counting into a single circuit block, enhancing efficiency. The digital integer PLL includes a comparator that forces the phase difference between the reference clock and feedback signals to approach zero, allowing for varied frequency tracking behavior by adjusting the duty cycle of the feedback signal.

Career Highlights

Shuo-Wei Chen has worked with prominent companies in the technology sector, including Qualcomm Incorporated and Qualcomm Atheros Inc. His experience in these organizations has contributed to his expertise in digital PLL technologies.

Collaborations

Shuo-Wei Chen has collaborated with David Kuochieh Su, further enhancing his work in the field of digital PLLs.

Conclusion

Shuo-Wei Chen's innovations in fractional and integer PLL architectures demonstrate his significant impact on the field of digital electronics. His contributions continue to influence advancements in frequency generation and counting technologies.