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For the Inventor, By the Inventor

San Francisco, CA, United States of America

Sherman H Yip

This inventor holds 23 USPTO granted patents and 1 published patent application, primarily in Speculative Processing. Top assignees: Oracle America, Inc., Sun Microsystems, Inc., Oracle International Corporation. Active years: 2007-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sherman H Yip. Retrieved from https://idiyas.com/inventor/sherman-h-yip

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 23 

% Patents Active = 100.0

Average Co-Inventor Count = 2.9

ph-index = 9

Forward Citations = 349(Granted Patents)


Location History:

  • San Francisco, CA (US) (2007 - 2015)
  • Sunnyvale, CA (US) (2011 - 2015)

Company Filing History:

goldMedal11 out of 1,928 
 
Oracle America, Inc.
 patents
silverMedal10 out of 7,642 
 
Sun Microsystems, Inc.
 patents
bronzeMedal2 out of 11,917 
 
Oracle International Corporation
 patents

Years Active: 2007-2015

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Areas of Expertise:
Speculative Execution
Pipeline Restart
Transactional Memory
Cache Management
Checkpoint Allocation
Instruction Execution
Performance Measurement
Data Return Handling
SIMD Conditional Moves
Failure Recovery
Artificial Register Dependency
Memory Latency
23 patents (USPTO):Explore Patents
1. 9086889 - Reducing pipeline restart penalty (2015-07-21),
2. 8984264 - Precise data return handling in speculative processors (2015-03-17),
3. 8732438 - Anti-prefetch instruction (2014-05-20),
4. 8688963 - Checkpoint allocation in a speculative processor (2014-04-01),
5. 8572356 - Space-efficient mechanism to support additional scouting in a processor using checkpoints (2013-10-29),
6. 8364900 - Pseudo-LRU cache line replacement for a high-speed cache (2013-01-29),
7. 8327188 - Hardware transactional memory acceleration through multiple failure recovery (2012-12-04),
8. 8316366 - Facilitating transactional execution in a processor that supports simultaneous speculative threading (2012-11-20),
9. 8181002 - Merging checkpoints in an execute-ahead processor (2012-05-15),
10. 8065485 - Method and apparatus for determining cache storage locations based on latency requirements (2011-11-22),
11. 8041900 - Method and apparatus for improving transactional memory commit latency (2011-10-18),
12. 7757068 - Method and apparatus for measuring performance during speculative execution (2010-07-13),
13. 7716457 - Method and apparatus for counting instructions during speculative execution (2010-05-11),
14. 7650487 - Method and structure for coordinating instruction execution in out-of-order processor execution using an instruction including an artificial register dependency (2010-01-19),
15. 7634639 - Avoiding live-lock in a processor that supports speculative execution (2009-12-15),

Title: The Innovative Journey of Sherman H Yip

Introduction: Sherman H Yip, a distinguished inventor based in San Francisco, CA, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: Sherman H Yip holds several patents in the areas of artificial intelligence, renewable energy, and biotechnology, showcasing his diverse range of expertise and creativity.

Career Highlights: With a career spanning over two decades, Sherman H Yip has worked with leading tech companies, research institutions, and universities, playing a pivotal role in developing cutting-edge solutions that have revolutionized various industries.

Collaborations: Throughout his career, Sherman H Yip has collaborated with top scientists, engineers, and researchers from around the world, fostering a culture of innovation and excellence in all his projects.

Conclusion: Sherman H Yip's passion for innovation, coupled with his relentless drive to push the boundaries of technology, has established him as a visionary inventor whose work continues to inspire and shape the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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