Shengwen Xiang

Title: Innovations of Shengwen Xiang in SerDes Technology.

Introduction

Shengwen Xiang is a notable inventor based in Shenzhen, China. He has made significant contributions to the field of SerDes technology, particularly with his innovative designs that enhance data transmission efficiency.

Latest Patents

Shengwen Xiang holds a patent for a "SerDes module clock network architecture." This invention comprises a reference clock input port, multiple data transmission channels, several user logic interfaces, frequency division branches, and a phase locked loop. The architecture allows the reference clock input port to receive an input clock and convey it to the phase locked loop. The phase locked loop then outputs a PLL output clock signal, which is distributed to the data transmission channels and frequency division branches. After frequency division, user interface clocks are output and conveyed to the user logic interfaces. This design is particularly beneficial when the PLL output clock signal is provided to an internal dedicated channel, allowing for efficient signal output to user logic interfaces for use by an FPGA.

Career Highlights

Shengwen Xiang is currently employed at Shenzhen Pango Microsystems Co., Ltd. His work at this company has been instrumental in advancing the capabilities of SerDes technology, making significant strides in the efficiency and reliability of data transmission systems.

Collaborations

Shengwen collaborates with Ying Liu, a coworker who shares his commitment to innovation in the field. Their partnership has fostered a creative environment that encourages the development of cutting-edge technologies.

Conclusion

Shengwen Xiang's contributions to SerDes technology through his innovative patent demonstrate his expertise and commitment to advancing the field. His work continues to influence the landscape of data transmission, showcasing the importance of innovation in technology.