Wuxi, China

Sheng Ding

This inventor holds 1 USPTO granted patent. Top assignee: Jiangnan University. Active years: 2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sheng Ding. Retrieved from https://idiyas.com/inventor/sheng-ding-bj7ctda2

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1


Company Filing History:


Years Active: 2019

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1 patent (USPTO):Explore Patents

Title: Sheng Ding - Innovator in High Voltage Protection Devices

Introduction

Sheng Ding is a notable inventor based in Wuxi, China. He has made significant contributions to the field of electrical engineering, particularly in the development of high voltage protection devices. His innovative work focuses on enhancing the robustness and reliability of integrated circuits.

Latest Patents

Sheng Ding holds a patent for an "Embedded high voltage LDMOS-SCR device with a strong voltage clamp and ESD robustness." This invention provides an effective solution for on-chip electrostatic discharge (ESD) protection in high voltage integrated circuits. The device features a complex structure that includes various regions and gates designed to improve ESD robustness and voltage clamp capability.

Career Highlights

Sheng Ding is affiliated with Jiangnan University, where he continues to advance his research and development efforts. His work has garnered attention for its practical applications in the electronics industry, particularly in enhancing the safety and performance of high voltage ICs.

Collaborations

Sheng Ding has collaborated with notable colleagues, including Hailian Liang and Huyun Liu. Their combined expertise contributes to the innovative projects undertaken at Jiangnan University.

Conclusion

Sheng Ding's contributions to the field of high voltage protection devices exemplify the importance of innovation in electrical engineering. His patent reflects a commitment to improving the safety and efficiency of integrated circuits.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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