Lucknow, India

Shashank Dabral

This inventor holds 2 USPTO granted patents. Top assignee: Other. Active years: 2007-2008.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shashank Dabral. Retrieved from https://idiyas.com/inventor/shashank-dabral-fj0riak2

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 3.1

ph-index = 2

Forward Citations = 8(Granted Patents)


Location History:

  • Lucknow, IN (2007)
  • Lucknow, Uttar Pradesh, IN (2008)

Company Filing History:

goldMedal2 out of 834,570 
Other
 patents

Years Active: 2007-2008

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2 patents (USPTO):Explore Patents

Title: Innovations of Shashank Dabral

Introduction

Shashank Dabral is an accomplished inventor based in Lucknow, Uttar Pradesh, India. He has made significant contributions to the field of data architecture and embedded systems. With a total of 2 patents, his work focuses on enhancing data transfer efficiency and system design.

Latest Patents

One of his latest patents is titled "Data packing in a 32-bit DMA architecture." This invention presents a method for reducing data transfer overheads in a 32-bit bus interface unit direct memory access architecture. The method involves identifying the optimal number of data elements that can be accessed as a single full-word transfer. It sets data packing criteria, analyzes data patterns, and determines the impact of offset direction on data packing. If the packing criteria are met, data is compacted and fetched in four bytes or two half-words in one transaction, thereby performing a full-word transfer instead of a partial transfer. If the criteria are not met, a single byte or half-word is fetched. This invention provides a system that includes an external address generation unit for generating external memory addresses and corresponding byte enables, along with a read local address generation unit for generating internal memory addresses.

Another notable patent is "Configurable components for embedded system design." This invention outlines a system and method for designing an accelerator for a processor-based system. The design problem is partitioned into a data communication module design problem and a data compute core module design problem. The hardware design of the data communication module is achieved through a predetermined communication template customized for specific applications. This template includes configurable communication components and a programmable control flow path, which enhances the speed of data transfer and control processes in the accelerator.

Career Highlights

Shashank Dabral has demonstrated a strong commitment to innovation in technology. His work has significantly impacted the efficiency of data handling in embedded systems. His inventions are a testament to his expertise and dedication to advancing technology.

Collaborations

Shashank has collaborated with notable colleagues, including Ramanujan K Valmiki and Ashok Halambi. These partnerships have contributed to the development and refinement of his innovative ideas.

Conclusion

Shashank Dabral is a prominent inventor whose work in data architecture and embedded systems has led to significant advancements. His patents reflect his innovative spirit and commitment to improving technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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