Noida, India

Sarvesh Verma

This inventor holds 1 USPTO granted patent. Top assignee: Freescale Semiconductor,inc.. Active years: 2013.


Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2013

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1 patent (USPTO):Explore Patents

Title: Innovations by Sarvesh Verma in Electronic Circuit Design

Introduction

Sarvesh Verma is a notable inventor based in Noida, India. He has made significant contributions to the field of electronic circuit design. His innovative approach has led to the development of a unique patent that addresses challenges in circuit layout planning.

Latest Patents

Sarvesh Verma holds a patent for a method titled "Scan chain re-ordering in electronic circuit design based on region congestion in layout plan." This invention focuses on improving the efficiency of electronic circuit designs by identifying congestion areas on a congestion map. The method involves determining a routing preference for each congestion area, forming scan cells into segments, and reordering these segments based on the identified routing preferences. This innovation enhances the overall performance and reliability of electronic circuits.

Career Highlights

Sarvesh Verma is currently employed at Freescale Semiconductor, Inc., where he applies his expertise in electronic design automation. His work at Freescale has allowed him to collaborate with other talented professionals in the industry, further advancing his knowledge and skills.

Collaborations

One of his notable coworkers is Vishal Gupta, with whom he has likely shared insights and experiences in the field of electronic circuit design.

Conclusion

Sarvesh Verma's contributions to electronic circuit design through his innovative patent demonstrate his commitment to advancing technology. His work not only addresses current challenges but also paves the way for future developments in the industry.

Profile summary based on public USPTO records.
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