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Aberdeen, NJ, United States of America

Rong Pan

This inventor holds 5 USPTO granted patents. Top assignee: Lsi Logic Corporation. Active years: 1998-1999.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Rong Pan. Retrieved from https://idiyas.com/inventor/rong-pan-foiyli1t

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 5

% Patents Active = 100.0

Average Co-Inventor Count = 3.3

ph-index = 4

Forward Citations = 133(Granted Patents)

Location History:

Aberdeen, NJ (US) (1998 - 1999)
Stanford, CA (US) (1999)

Company Filing History:

Lsi Logic Corporation

Years Active: 1998-1999

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5 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 5956370 - Wrap-back test system and method (1999-09-21),

2. 5896426 - Programmable synchronization character (1999-04-20),

3. 5790563 - Self test of core with unpredictable latency (1998-08-04),

4. 5787114 - Loop-back test system and method (1998-07-28),

5. 5781038 - High speed phase locked loop test method and means (1998-07-14),

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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