East Petersburg, PA, United States of America

Ronald S Pennypacker

This inventor holds 1 USPTO granted patent. Top assignee: Rca Inc.. Active years: 1981.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ronald S Pennypacker. Retrieved from https://idiyas.com/inventor/ronald-s-pennypacker

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 47(Granted Patents)


Company Filing History:


Years Active: 1981

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1 patent (USPTO):Explore Patents

Title: Ronald S. Pennypacker and Semiconductor Imager Manufacturing

Introduction

Ronald S. Pennypacker is an inventor associated with East Petersburg, Pennsylvania, and RCA Inc. His recorded patent concerns a manufacturing method for producing thinned-substrate imagers.

Latest Patents

Pennypacker is credited with 1 patent, titled “Manufacture of Thinned Substrate Imagers.” The invention describes protecting the front surface and peripheral edge of a semiconductor wafer, then chemically thinning the central region of its back surface to a desired thickness. A glass sheet is fitted into the thinned region and bonded to the wafer, forming a laminated structure. Individual imager devices are then separated by cutting through the glass and thinned substrate along the lines between devices.

Career Highlights

Pennypacker’s documented patent work addresses a practical fabrication process for semiconductor imagers. The method combines controlled wafer thinning, glass reinforcement, and device separation in a sequence designed to produce individual imager devices.

Collaborations

Thomas William Edwards is identified as Pennypacker’s coworker. The available information does not specify his role in the patent or the invention.

Conclusion

Ronald S. Pennypacker’s recorded invention focuses on a wafer-thinning and glass-lamination process for manufacturing semiconductor imagers, reflecting his documented contribution to semiconductor fabrication.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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