Bernin, France

Romain Bouveyron

This inventor holds 1 USPTO granted patent and 1 published patent application and 1 EPO patent. Top assignee: Soitec. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Romain Bouveyron. Retrieved from https://idiyas.com/inventor/romain-bouveyron

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Romain Bouveyron: Inventor in Semiconductor Technology.

Introduction

Romain Bouveyron is an inventor based in Bernin, France. His patent work concerns carrier substrates for silicon-on-insulator (SOI) structures, a technology used in semiconductor manufacturing.

Latest Patents

The provided information lists one patent associated with Bouveyron: “Carrier Substrate for SOI Structure and Associated Manufacturing Method.” The patent describes a carrier substrate comprising monocrystalline silicon, with front and back faces, and a method for manufacturing such a substrate. The available description does not provide further details about its structure or manufacturing steps.

Career Highlights

Bouveyron is associated with Soitec, a company specializing in semiconductor materials and technologies. His listed patent reflects work on substrate design and manufacturing for SOI structures. He is credited with 1 patent in the information provided.

Collaborations

Isabelle Bertrand is identified as Bouveyron’s coworker. The supplied information does not specify her role in the patent or describe any direct collaboration between them.

Conclusion

Romain Bouveyron’s listed invention focuses on a monocrystalline-silicon carrier substrate and its manufacturing method, connecting his patent work with Soitec’s semiconductor technology activities.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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