Celina, TX, United States of America

Robert John Porter

This inventor holds 1 USPTO granted patent. Top assignee: Hewlett-Packard Development Company, L.p.. Active years: 2004.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Robert John Porter. Retrieved from https://idiyas.com/inventor/robert-john-porter

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 24(Granted Patents)


Company Filing History:


Years Active: 2004

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1 patent (USPTO):Explore Patents

Title: Robert John Porter and Semiconductor Verification

Introduction

Robert John Porter is an inventor associated with Celina, Texas, and Hewlett-Packard Development Company, L.P. His patent work addresses automated verification of semiconductor-device test plans.

Latest Patents

Porter is associated with 1 patent, titled “System and Method for Evaluating Functional Coverage Linked to a Verification Test Plan.” The invention describes a system for automatically checking a semiconductor device’s test plan against verification events. It uses a test-plan tool and database to record test items, a monitor generator to detect functional coverage during verification, and an evaluator to compare events with planned items, assess completeness, and update the database.

Career Highlights

The patent reflects work at the intersection of hardware description models, verification testing, and functional coverage. Its approach links test-plan definitions with observed verification results to help identify whether planned test items have been addressed.

Collaborations

Porter’s listed coworkers include Harry David Foster and Nathan Dirk Zelle.

Conclusion

Robert John Porter’s patent documents a method for connecting semiconductor verification results to test-plan coverage, supporting more systematic evaluation of test completeness.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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