Austin, TX, United States of America

Robert Hayosh

This inventor holds 1 USPTO granted patent. Top assignee: International Business Machines Corporation. Active years: 1998.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Robert Hayosh. Retrieved from https://idiyas.com/inventor/robert-hayosh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 7(Granted Patents)


Company Filing History:


Years Active: 1998

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1 patent (USPTO):Explore Patents

Title: Robert Hayosh and His Patent for Bit Extraction

Introduction

Robert Hayosh is an inventor associated with Austin, Texas, and International Business Machines Corporation. His patent work addresses a logic-circuit technique for extracting bits used in binary-number truncation and rounding.

Latest Patents

The provided information lists one patent for Hayosh: “Least Significant Bit and Guard Bit Extractor.” The invention uses an intermediate signal from a mask generator and an exclusive-OR operation on adjacent bits to create a second mask near the boundary between bits retained and bits dropped during truncation. Applying that mask to overlapping groups of bits allows the circuit to extract the least significant bit and guard bit. The method can move extraction off the processor’s critical path and let it proceed in parallel with shifting.

Career Highlights

Hayosh’s listed patent reflects work on processor logic and efficient binary-number processing. His association with International Business Machines Corporation connects this invention to the company’s research and development in computing technology.

Collaborations

The provided information names Roland A. Bechade and Stephen Gerard Shuma as Hayosh’s coworkers. It does not specify their roles in the patent or whether they collaborated directly on the invention.

Conclusion

Robert Hayosh’s listed patent presents a technique for extracting key bits during truncation and rounding, with the aim of improving processor efficiency by enabling parallel processing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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