Wappingers Falls, NY, United States of America

Rajesh Gupta

This inventor holds 2 USPTO granted patents. Top assignee: International Business Machines Corporation. Active years: 1995-1998.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Rajesh Gupta. Retrieved from https://idiyas.com/inventor/rajesh-gupta-8sw689ox

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 54(Granted Patents)


Location History:

  • Wappingers Falls, NY (US) (1995)
  • Poughkeepsie, NY (US) (1998)

Company Filing History:


Years Active: 1995-1998

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2 patents (USPTO):Explore Patents

Title: Innovations by Rajesh Gupta

Introduction

Rajesh Gupta is a notable inventor based in Wappingers Falls, NY (US). He has made significant contributions to the field of integrated circuit design, holding 2 patents that showcase his innovative approach to technology.

Latest Patents

One of his latest patents is titled "Chip sizing for hierarchical designs." This patent discloses a method for resizing the macro cells' boundaries of an integrated chip, which becomes effective after the initial floorplanning process has been completed. The method apportions any excess area that is freed up after the initial floorplanning process by altering the sizes or dimensions of the macro cell within the hierarchy of the integrated circuit. This alteration ensures that the fractional change in the percentage occupancy remains substantially constant among all macro cells at all hierarchy levels.

Another significant patent is "Method of target generation for multilevel hierarchical circuit designs." This invention focuses on generating delay targets for creating a multilevel hierarchical circuit design. It involves providing a hierarchical design description and delay constraints of the circuit design, generating a net measure for each net and macro cell, and creating an abstract delay model for each macro cell based on the design description. The process culminates in generating delay targets for the nets and macro cells, which are essential for the successful creation of the circuit design.

Career Highlights

Rajesh Gupta is currently employed at International Business Machines Corporation (IBM), where he continues to innovate and contribute to advancements in technology. His work at IBM has allowed him to apply his expertise in integrated circuit design and further develop his patented methods.

Collaborations

Throughout his career, Rajesh has collaborated with notable colleagues, including Jitendra Apte and John Youssef Sayah. These collaborations have fostered an environment of innovation and creativity, leading to the development of cutting-edge technologies.

Conclusion

Rajesh Gupta's contributions to integrated circuit design through his patents reflect his dedication to innovation in technology. His work at IBM and collaborations with esteemed colleagues further enhance his impact in the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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