New Delhi, India

Rajesh Bansal

This inventor holds 1 USPTO granted patent. Top assignee: Freescale Semiconductor,inc.. Active years: 2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Rajesh Bansal. Retrieved from https://idiyas.com/inventor/rajesh-bansal-r3t6lfci

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1


Company Filing History:


Years Active: 2012

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1 patent (USPTO):Explore Patents

Title: Rajesh Bansal: Innovator in Semiconductor Technology

Introduction

Rajesh Bansal is a prominent inventor based in New Delhi, India. He has made significant contributions to the field of semiconductor technology. His innovative work has led to the development of a unique patent that enhances the efficiency of semiconductor dies.

Latest Patents

Rajesh Bansal holds a patent for a semiconductor die that includes a first set of metal lines and a second set of metal lines. The first and second sets of metal lines are placed in alternate planes and are orthogonal to each other. A via is utilized to connect a first metal line from the first set with a second metal line from the second set. The via location is offset, ensuring that a side of the first metal line aligns with a side of the second metal line. This design allows a metal line adjacent to the first metal line to avoid detouring around the via. He has 1 patent to his name.

Career Highlights

Rajesh Bansal is currently employed at Freescale Semiconductor, Inc., where he continues to innovate in the semiconductor industry. His work has been instrumental in advancing semiconductor technology and improving manufacturing processes.

Collaborations

Some of his notable coworkers include Pankaj K Jha and Chetan Verma. Their collaboration has contributed to the success of various projects within the company.

Conclusion

Rajesh Bansal is a key figure in semiconductor innovation, with a focus on enhancing the design and functionality of semiconductor dies. His contributions are paving the way for future advancements in the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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