Sunnyvale, CA, United States of America

Rajendra D Pendse

This inventor holds 1 USPTO granted patent. Top assignee: National Semiconductor Corporation. Active years: 1991.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Rajendra D Pendse. Retrieved from https://idiyas.com/inventor/rajendra-d-pendse-3oujcpyx

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 14(Granted Patents)


Company Filing History:


Years Active: 1991

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1 patent (USPTO):Explore Patents

Title: Innovations by Rajendra D Pendse

Introduction

Rajendra D Pendse is a notable inventor based in Sunnyvale, California. He has made significant contributions to the field of integrated circuit packaging. His work focuses on enhancing the performance and reliability of electronic components.

Latest Patents

Rajendra D Pendse holds a patent for a "Stress reduction package and process." This innovative design features an integrated circuit package that includes a layer of silicon positioned between the copper die attach pad and the silicon integrated circuit die. The layer is designed to be about half the thickness of the silicon die and extends symmetrically beyond it. This extension provides a horizontal surface for thermosetting encapsulating resin to adhere, which enhances stress reduction. Additionally, the vertical edges of the layer help prevent stress on the die by resisting forces from the encapsulating resin during curing. He has 1 patent to his name.

Career Highlights

Rajendra D Pendse is associated with National Semiconductor Corporation, where he has contributed to various projects aimed at improving semiconductor technology. His expertise in integrated circuit packaging has been instrumental in advancing the company's product offerings.

Collaborations

One of his notable coworkers is Jeffrey C Demmin, with whom he has likely collaborated on various projects within the company.

Conclusion

Rajendra D Pendse's innovative work in integrated circuit packaging demonstrates his commitment to enhancing electronic component reliability. His contributions continue to impact the field positively.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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