R Iris Bahar

Title: R Iris Bahar: Innovator in Multi-Processor Systems

Introduction

R Iris Bahar is a notable inventor based in Belmont, MA, who has made significant contributions to the field of computer architecture. With a focus on enhancing the efficiency of multi-processor systems, Bahar's work has led to innovative solutions that improve processing speed and reliability.

Latest Patents

Bahar holds a patent for an "Error transition mode for multi-processor system." This invention describes a pipelined CPU that executes variable-length instructions while referencing memory with various data widths. The patent emphasizes macroinstruction pipelining, which allows for flexibility in instruction execution times. It features a wide bandwidth for memory access, fetching 64-bit data blocks on each cycle. The hierarchical cache arrangement improves cache set selection, increasing the likelihood of cache hits. Additionally, the invention incorporates a writeback cache and a sophisticated branch prediction method that utilizes a branch history table to enhance processing efficiency.

Career Highlights

Bahar has worked at Digital Equipment Corporation, where he has contributed to various projects that focus on advancing computer technology. His expertise in processor design and architecture has positioned him as a key figure in the development of innovative computing solutions.

Collaborations

Bahar has collaborated with notable colleagues, including Rebecca L Stamm and Michael A Callander, who have also contributed to advancements in the field of computer engineering.

Conclusion

R Iris Bahar's contributions to multi-processor systems through his innovative patent demonstrate his commitment to enhancing computer architecture. His work continues to influence the industry and pave the way for future advancements in technology.