Chandler, AZ, United States of America

Qiang Li

This inventor holds 1 USPTO granted patent and 3 published patent applications. Top assignees: Battelle Energy Alliance, LLC, Eck Industries, Inc., Iowa State University Research Foundation Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Qiang Li. Retrieved from https://idiyas.com/inventor/qiang-li-1mrnem94

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Qiang Li - Innovator in Integrated Circuit Technology

Introduction

Qiang Li is an inventor based in Chandler, AZ (US), known for his contributions to the field of integrated circuit technology. His work focuses on innovative solutions that enhance the performance and reliability of semiconductor devices. Although he currently holds no granted patents, his latest patent applications reflect his commitment to advancing technology in this area.

Latest Patent Applications

1. **THROUGH GLASS VIAS WITH COMPLIANT LAYER FOR INTEGRATED CIRCUIT DEVICE PACKAGES** - This application describes integrated circuit (IC) die packages that include a glass with conductive through-glass vias (TGVs). The TGVs are lined with a buffer made of an inorganic material that has a low elastic (Young's) modulus. This buffer accommodates internal stress between the glass and the metallization formed over it. The compliant inorganic material may be a metal or metal alloy, different from the via metallization. Additionally, the inorganic material may include metal nitrides, metal silicides, or metal carbides. A TGV buffer may consist of one material layer within a stack of two or more layers deposited on TGV sidewall surfaces. A routing structure can be built on at least one side of the glass, with IC die assembled to this structure. The buffer present within the TGVs may not be included in the metal features of the routing structure.

2. **INTERVENING LAYERS FOR THRU-VIA SEED METALLIZATION** - This application involves a semiconductor substrate that features a glass layer with a first and second major surface. It includes at least one electrical transmission through hole extending from the first major surface to the second major surface, along with an intervening layer coupled with at least one of these surfaces and the electrical transmission through hole. The intervening layer comprises metal, silicon, and oxygen, with a metal layer bonded to it.

Conclusion

Qiang Li's innovative approaches in his latest patent applications demonstrate his dedication to improving integrated circuit technology. His work has the potential to significantly impact the semiconductor industry, paving the way for future advancements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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