Bengaluru, India

Pradeep Dasari

This inventor holds 1 USPTO granted patent. Top assignee: Sandisk Technologies Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Pradeep Dasari. Retrieved from https://idiyas.com/inventor/pradeep-dasari

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Pradeep Dasari and Memory Read-Method Innovation.

Introduction

Pradeep Dasari is an inventor based in Bengaluru, India, whose patent work addresses the reliability of non-volatile memory. He is associated with SanDisk Technologies Inc. His listed portfolio includes 1 patent.

Latest Patents

Dasari’s patent, “Read Method Enhancement to Reduce Read Disturb in Mixed-Mode Memory Storage Regions,” describes a non-volatile storage system with memory elements and control circuitry. The circuitry accesses device parameters for different storage-region types, then uses the corresponding parameters to perform memory operations. This approach is designed to reduce read disturb when operating across mixed-mode storage regions.

Career Highlights

The available information connects Dasari’s work with SanDisk Technologies Inc. and highlights his contribution to memory-storage technology through the patented read-method enhancement.

Collaborations

The listed coworkers associated with Dasari include Harvijay Singh and Xiang Yang. Their names provide context for the collaborative environment surrounding this memory-technology work.

Conclusion

Pradeep Dasari’s patent focuses on improving read operations in mixed-mode non-volatile memory, with the goal of reducing read disturb through storage-region-specific device parameters.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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