This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2026.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2026
Title: PO-Chin Nien: Semiconductor Process Innovation
Introduction
PO-Chin Nien is an inventor associated with Hsinchu, Taiwan, and Taiwan Semiconductor Manufacturing Co., Ltd. His patent work addresses impurity removal during chemical mechanical planarization, a process used in semiconductor manufacturing.
Latest Patents
The provided information identifies one patent associated with Nien: “System and Method for Removing Impurities During Chemical Mechanical Planarization.” The invention describes a system with a rotating polishing pad, a wafer held against the pad by a planarization head, a slurry supply system, and a pad conditioner. An impurity removal system removes debris and other impurities from the slurry during the process. Nien is credited with 1 patent in the supplied data.
Career Highlights
Nien’s listed patent reflects work on improving chemical mechanical planarization by addressing contamination in the slurry. The supplied information associates him with Taiwan Semiconductor Manufacturing Co., Ltd., a semiconductor company based in Taiwan.
Collaborations
Chih Hung Chen is identified as Nien’s coworker. The provided details do not specify their roles or describe a particular joint project.
Conclusion
PO-Chin Nien’s listed invention focuses on removing impurities during chemical mechanical planarization, highlighting a practical approach to supporting semiconductor wafer processing.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile