Santa Clara, CA, United States of America

Piyush Patel

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Nvidia Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Piyush Patel. Retrieved from https://idiyas.com/inventor/piyush-patel-3f5i7po1

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Piyush Patel: Innovator in Multi-Dielet Processor Architectures

Introduction

Piyush Patel is a notable inventor based in Santa Clara, CA. He has made significant contributions to the field of processor architectures, particularly in the area of memory management. His innovative work has implications for the performance and efficiency of graphics and compute engines.

Latest Patents

Piyush Patel holds a patent titled "Synchronizing memory management units in multi-dielet processor architectures." This patent describes a method for supporting distributed graphics and compute engines in a multi-dielet parallel processing system. The architecture involves synchronizing memory management in such systems, where each dielet is equipped with a memory management unit (MMU). The processing of memory-related messages is serialized by a designated MMU, ensuring efficient communication across dielets.

Career Highlights

Piyush Patel is currently employed at Nvidia Corporation, a leading company in the field of graphics processing and computing technology. His role at Nvidia allows him to work on cutting-edge technologies that push the boundaries of what is possible in graphics and computing.

Collaborations

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Conclusion

Piyush Patel's contributions to multi-dielet processor architectures exemplify the innovative spirit of modern technology. His work continues to influence advancements in graphics and compute engines, showcasing the importance of effective memory management in complex systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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