Hsinchu, Taiwan

Ping-Huang Chiang

This inventor holds 2 USPTO granted patents. Top assignee: Industrial Technology Research Institute. Active years: 1997-1999.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ping-Huang Chiang. Retrieved from https://idiyas.com/inventor/ping-huang-chiang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 3.4

ph-index = 2

Forward Citations = 223(Granted Patents)


Company Filing History:


Years Active: 1997-1999

Loading Chart...
2 patents (USPTO):Explore Patents

Title: Ping-Huang Chiang and Semiconductor Packaging Innovations.

Introduction

Ping-Huang Chiang is an inventor based in Hsinchu, Taiwan. His patent work focuses on semiconductor packaging, including heat management and solder-paste alignment. He is associated with the Industrial Technology Research Institute and has 2 patents.

Latest Patents

Chiang’s listed patents address practical challenges in assembling and improving integrated-circuit packages.

“Structure for Semiconductor Package for Improving the Efficiency of” describes a package structure designed to improve heat dissipation. It combines a substrate with an opening, a heat spreader featuring a patterned underside, and a chip mounted on the spreader. A supporting member and encapsulating material complete the assembly, while preformed solder balls are attached beneath the substrate.

“Solder Paste Inter-Layer Alignment Apparatus for Area-Array On-Board” presents an apparatus for applying and aligning solder paste with corresponding pads on an integrated-circuit package carrier. A thin, electrically insulating layer resists high temperatures and solder wetting, and its apertures guide the solder paste into position. Removable film tape temporarily holds the paste in the apertures.

Career Highlights

Chiang’s listed inventions reflect work on two complementary aspects of semiconductor packaging: managing heat around a chip and accurately positioning solder paste during package assembly. Both designs focus on structural features intended to support reliable manufacturing and interconnection.

Collaborations

The provided information identifies Yu-Kon Chou and Lung-Tai Chen as Chiang’s coworkers. It does not specify their roles in the listed patents.

Conclusion

Ping-Huang Chiang’s patent portfolio highlights semiconductor packaging innovations in thermal management and solder-paste alignment, developed in connection with the Industrial Technology Research Institute.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…