Company Filing History:
Years Active: 2001
Title: Pierre Yves Challier: Innovator in ASIC Testing and Verification
Introduction
Pierre Yves Challier is a notable inventor based in Cagnes sur Mer, France. He has made significant contributions to the field of ASIC (Application-Specific Integrated Circuit) design and verification. His innovative work focuses on enhancing the testing and verification processes of complex electronic systems.
Latest Patents
Challier holds a patent for an "HDL simulation interface for testing and verifying an ASIC model." This invention provides an interface system that allows for the testing and verification of ASIC designs at various levels of abstraction. The system is implemented as software that runs on a computer, enabling the execution of a model of the ASIC, a simulator, and a test interface. The model is created using Hardware Description Language (HDL) and includes both a logic entity and a processor entity. The simulator is designed to test this model, while the test interface facilitates communication between the model and the simulator, allowing for the observation of register status information during simulation.
Career Highlights
Challier is associated with VLSI Technology, Inc., where he applies his expertise in ASIC design and verification. His work has contributed to advancements in the efficiency and reliability of electronic systems.
Collaborations
Challier has collaborated with notable colleagues such as Christelle Faucon and Jean Francois Duboc, enhancing the innovative environment at VLSI Technology, Inc.
Conclusion
Pierre Yves Challier's contributions to ASIC testing and verification exemplify the importance of innovation in the electronics industry. His patent and collaborative efforts continue to influence the development of advanced electronic systems.