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For the Inventor, By the Inventor

Alameda, CA, United States of America

Peter Tze-Hwa Liu

This inventor holds 13 USPTO granted patents. Top assignee: Marvell International Limited. Active years: 2010-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Peter Tze-Hwa Liu. Retrieved from https://idiyas.com/inventor/peter-tze-hwa-liu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 13

% Patents Active = 46.2

Average Co-Inventor Count = 1.6

ph-index = 4

Forward Citations = 40(Granted Patents)


Company Filing History:

goldMedal13 out of 5,162 
 
Marvell International Limited
 patents

Years Active: 2010-2017

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13 patents (USPTO):Explore Patents
1. 9582356 - System and method for DDR memory timing acquisition and tracking (2017-02-28),
2. 8935596 - System and methods for storing data encoded with error information in a storage medium (2015-01-13),
3. 8654874 - Method and apparatus for detecting impulse noise (2014-02-18),
4. 8484273 - Processing system and method for transform (2013-07-09),
5. 8352837 - System and methods for storing data encoded with error information in a storage medium (2013-01-08),
6. 8325828 - Method and apparatus for detecting impulse noise (2012-12-04),
7. 8139472 - Bit swap architecture in digital subscriber line communication systems (2012-03-20),
8. 8132076 - Method and apparatus for interleaving portions of a data block in a communication system (2012-03-06),
9. 8094710 - Wide band noise early detection and protection architecture for a frequency domain equalizer (2012-01-10),
10. 8046659 - Erasure forecasting and error-correction strategies (2011-10-25),
11. 7698619 - Erasure forecasting and error-correction strategies (2010-04-13),
12. 7676532 - Processing system and method for transform (2010-03-09),
13. 7644340 - General convolutional interleaver and deinterleaver (2010-01-05),

Title: Innovations of Peter Tze-Hwa Liu

Introduction

Peter Tze-Hwa Liu is a prominent inventor based in Alameda, CA (US). He has made significant contributions to the field of memory technology, holding a total of 13 patents. His work focuses on enhancing memory access performance and data storage methods.

Latest Patents

One of his latest patents is titled "System and method for DDR memory timing acquisition and tracking." This invention describes systems and methods for providing real-time closed-loop control of memory access. The method involves accessing a memory of a computing device during its real-time operation and detecting bit errors associated with this access. It generates a performance metric based on the detected bit errors and adjusts the settings of timing elements to maintain optimal memory access performance.

Another notable patent is "System and methods for storing data encoded with error information in a storage medium." This invention provides a method for storing binary data along with encoded binary error signals. The encoded signals represent the occurrence of errors in the binary data. The method includes encoding the binary data and error signals to generate a binary codeword signal, which is then stored and retrieved from a storage medium.

Career Highlights

Peter Tze-Hwa Liu is currently employed at Marvell International Limited, where he continues to innovate in the field of memory technology. His work has significantly impacted the efficiency and reliability of memory systems in computing devices.

Collaborations

Throughout his career, Peter has collaborated with notable colleagues, including Jacky S Chow and Jun Zhu. These collaborations have contributed to the advancement of technology in their respective fields.

Conclusion

Peter Tze-Hwa Liu's contributions to memory technology through his patents and work at Marvell International Limited highlight his role as a leading inventor in the industry. His innovations continue to shape the future of computing memory systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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